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At present, the vast majority of urban and rural residents in China use electricity to read meters. This backward way consumes a lot of manpower and material resources, and the time span for collecting data is large and the accuracy is low. Therefore, the relevant state departments will gradually use automatic meter reading systems instead of manual meter reading. However, in this way, traditional mechanical electricity meters cannot meet the requirements in terms of performance. Therefore, we adopt a single-chip automatic measurement and control technology, designed a centralized smart meter that can be used independently and can face the automatic meter reading system. In order to make it stable, safe and reliable for a long time, a comprehensive system anti-jamming design must be carried out. The following content will be introduced:
Necessity of system anti-jamming design
Because the centralized smart meter works in a residential area, it is vulnerable to various electrical and electromagnetic interferences inside and outside the system, with power system interference as the main reason. In household appliances, many of them are inductive loads, and their rapid switching will cause noise interference to the power grid, which may cause the data in the microcontroller to become confusing or dead. The rules are as follows:
(1) When the amplitude of the interference pulse is small, there is basically no effect on the microcontroller;
(2) When the amplitude of interference pulses is large, reset the microcontroller;
(3) The amplitude of the interference pulse is large, and there are many pulses at a moment, which may cause the data of the single-chip microcomputer to be confused or crash.
Smart meters require continuous operation for many years. Any anomalies (data corruption, crashes, etc.) that occur during the operation of the smart meters require that they be safely restored. Therefore, the anti-interference requirements are high. If no effective anti-jamming measures are taken, when the system encounters strong interference signals during the operation process, the reliability of its performance and the safety of the operation will be reduced, which will cause problems for the user, property management, or electrical industry. Large economic losses have even led to economic disputes.
The basic principles of anti-jamming design are: suppress interference sources, cut off the interference propagation path, and improve the anti-interference performance of sensitive devices. It can be seen that to ensure the safe and reliable operation of the smart meter system, an important link is the anti-jamming design of the SCM system, which mainly includes hardware anti-jamming and software anti-jamming.
System anti-jamming design Hardware anti-jamming design
The photoelectric signal coupler is used for the collection and output of the power signal. The primary and secondary sides of the optocoupler are electrically insulated. Therefore, they have a strong ability to suppress the interference of the ground potential, and they also have strong electromagnetic interference suppression. ability. When power is supplied to the system, the interference noise will be directly added to the control circuit by the power supply. The reset lines, interrupt lines, and other control lines of the microcontroller are most susceptible to this external noise, so they must be taken. Certain measures to suppress and eliminate this interference. The specific methods are: adding shields, isolation transformers, magnetic rings and π-shaped filter circuits, but these can only reduce the number and amplitude of interference pulses, and it is difficult to fundamentally solve them. Therefore, you must also use a dedicated microcontroller power supply monitoring chip to improve the anti-interference ability of sensitive devices.
A prominent feature of the system in the hardware anti-jamming is the use of the SCM system monitoring chip MAX691A, designed a CPU security monitoring circuit. The MAX691A features: reset, data memory write protection, backup battery switching, watchdog timer, and power monitor.
MAX691A main pin and its function description:
(1) VBATT: standby power input, can be connected to 3.6V lithium battery or charging circuit. If not, connect to GND.
(2) VOUT: Power output. When VCC is higher than the upper limit voltage, VOUT = VCC. When VCC is lower than the upper limit voltage, VOUT is connected to VBATT. A 0.1μF capacitor is required between VOUT and GND.
(3) VCC: working power access terminal, then +5V.
(4) GND: The power ground terminal is the reference point for all signals.
(5) PFI: Supply voltage comparator input. When this terminal voltage input is lower than 1.25V, PFO(--) will go low.
(6) PFO (————): Power-down output, active low. In Figure 1, it triggers the INT(--)0 interrupt, and the interrupt service routine will do emergency processing before powering down the system.
(7) WDI: watchdog feed end. When it remains high or low for 1.6s (typical), the internal watchdog timer overflows and triggers the WDO(---) signal output.
(8) CE (--) OUT: chip select signal output. Only when CE(--)IN is low and VCC is normal, CE(--)OUT outputs a low level, which can effectively prevent erroneous operation of the data memory.
(9) CE (--) IN: chip select signal input.
(10) WDO (——————): Watchdog output, active low. If WDI is vacant, WDO(——————) remains high.
(11) RESET (——————————): Active low reset terminal, when VCC is lower than 4.65V, RESET (——————————) becomes low level . The reset signal is typically 200ms.
(12) RESET: active high reset, open collector output.
In addition, MAX691A also has the function of oscillation frequency selection (7, 8 pins), which can adjust the time of reset and watchdog timer. In Fig. 1, a differential circuit and an inverter are added so that WDO (——————) directly triggers a system reset, which greatly simplifies the anti-jamming design of the software.
2. Software anti-interference design The software anti-jamming measures adopted by this system are as follows:
(1) Level detection instead of edge detection is applied to the input signal to reduce the effects of various random disturbance pulses.
(2) Back up the important state registration unit. After the system state is disturbed and disturbed, the information of the backup registration unit can be queried in time and the state can be corrected.
(3) Before storing the electricity data, check it to ensure the correctness of the data.
(4) The electricity data is stored in multiple locations in both the 6264 and 2465 and is backed up each other to ensure complete security.
(5) Set up the self-test program, set the status flag in some memory units, monitor it after starting operation, and ensure the high reliability of information storage, transmission and operation.
(6) Insert a null operation instruction: Insert a dummy instruction before comparing a conditional branch instruction, an absolute branch instruction, an interrupt, a stack instruction, and a data table to improve system stability.
(7) When the program is out of order and the data such as the program "runaway", data area, and working register is destroyed, take the following measures:
(a) Setting the monitoring tracking timer
Since the system is designed with a CPU safety monitoring circuit, the program can be monitored by using the watchdog (watchdog) of the MAX691A's timer interrupt. As long as the program is running normally, the timer will not have a timer interrupt. However, when the program is out of order and the WDI cannot be refreshed due to reasons such as “runawayâ€, the watchdog timer will cause a crash reset.
(b) Set up software traps
In the empty space of the program memory, the empty operation instruction and the long jump instruction (LJMPERR) are filled to intercept the runaway program, and finally the program is returned to the initial state by the software forced reset. During the software reset of the MCS-51 microcontroller, the interrupt return instruction, RETI, must be executed twice in succession to ensure that the interrupt flag is cleared and the system returns to normal. The error handler is as follows:
ERR:CLREA;correct software reset entry,off interrupt MOV66H,#0AAH;rebuild power on flag MOV67H,#55H
MOVDPTR, #ERR1; Prepare first return address PUSHDPL
PUSHDPH
RETI; Clear Advanced Interrupt Activation Flag ERR1:CLRA
PUSHACC
PUSHACC
RETI; Clear low-level interrupt active flag <br> <br> conclusion
The centralized smart meter system performs a comprehensive and effective system hardware and software anti-jamming design. In particular, it makes full use of the powerful monitoring function of the MAX691A chip to realize the three conditions (power-on, power-off, and crash) reset and data memory of the system. Write protection, backup battery switching, watchdog timing, and power monitoring. This greatly improves the ability of the system to resist strong interference, ensures the safety and reliability of the system operation, and provides a reliable technical guarantee for the practical application and promotion of the smart meter.
Analysis of Anti-interference Design of Centralized Smart Meter
introduction